Open-CMSIS-SVD  
System View Description
/device/cpu element

The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file is used to generate the device header file.

Example

<device>
...
<cpu>
<name>CM7</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<!-- has double precision FPU -->
<fpuPresent>true</fpuPresent>
<fpuDP>true</fpuDP>
<!-- has instruction and data cache -->
<icachePresent>true</icachePresent>
<dcachePresent>true</dcachePresent>
<!-- has no instruction nor data tighly coupled memory -->
<itcmPresent>false</itcmPresent>
<dtcmPresent>false</dtcmPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
...
<device>

This example describes a device based on a Cortex-M7 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and double precision hardware Floating Point Unit. It has a data cache and no instruction nor a tightly coupled memory. The Nested Vectored Interrupt Controller uses 4 bits to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by Arm.

/device/cpu

Parent Element Element Chain
device /device
Child Elements Description Type Occurrence
name The predefined tokens are:
  • CM0: Arm Cortex-M0
  • CM0PLUS: Arm Cortex-M0+
  • CM0+: Arm Cortex-M0+
  • CM1: Arm Cortex-M1
  • CM3: Arm Cortex-M3
  • CM4: Arm Cortex-M4
  • CM7: Arm Cortex-M7
  • CM23: Arm Cortex-M23
  • CM33: Arm Cortex-M33
  • CM35P: Arm Cortex-M35P
  • CM55: Arm Cortex-M55
  • CM85: Arm Cortex-M85
  • SC000: Arm Secure Core SC000
  • SC300: Arm Secure Core SC300
  • CA5: Arm Cortex-A5
  • CA7: Arm Cortex-A7
  • CA8: Arm Cortex-A8
  • CA9: Arm Cortex-A9
  • CA15: Arm Cortex-A15
  • CA17: Arm Cortex-A17
  • CA53: Arm Cortex-A53
  • CA57: Arm Cortex-A57
  • CA72: Arm Cortex-A72
  • SMC1: Arm China STAR-MC1
  • other: other processor architectures
cpuNameType 1..1
revision Define the HW revision of the processor. The version format is rNpM (N,M = [0 - 99]). revisionType 1..1
endian Define the endianness of the processor being one of:
  • little: little endian memory (least significant byte gets allocated at the lowest address).
  • big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
  • selectable: little and big endian are configurable for the device and become active after the next reset.
  • other: the endianness is neither little nor big endian.
endianType 1..1
mpuPresent Indicate whether the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0. boolean 1..1
fpuPresent Indicate whether the processor is equipped with a hardware floating point unit (FPU). Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0. boolean 1..1
fpuDP Indicate whether the processor is equipped with a double precision floating point unit. This element is valid only when <fpuPresent> is set to true. Currently, only Cortex-M7 processors can have a double precision floating point unit. boolean 0..1
dspPresent Indicates whether the processor implements the optional SIMD DSP extensions (DSP). Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional DSP extension. For ARMv7M SIMD DSP extensions are a mandatory part of Cortex-M4 and Cortex-M7. This tag is either set to true or false, 1 or 0.. This element is mandatory for Cortex-M33, Cortex-M35P and future processors with optional SIMD DSP instruction set. boolean 0..1
icachePresent Indicate whether the processor has an instruction cache. Note: only for Cortex-M7-based devices. boolean 0..1
dcachePresent Indicate whether the processor has a data cache. Note: only for Cortex-M7-based devices. boolean 0..1
itcmPresent Indicate whether the processor has an instruction tightly coupled memory. Note: only an option for Cortex-M7-based devices. boolean 0..1
dtcmPresent Indicate whether the processor has a data tightly coupled memory. Note: only for Cortex-M7-based devices. boolean 0..1
vtorPresent Indicate whether the Vector Table Offset Register (VTOR) is implemented in Cortex-M0+ based devices. This tag is either set to true or false, 1 or 0. If not specified, then VTOR is assumed to be present. boolean 0..1
nvicPrioBits Define the number of bits available in the Nested Vectored Interrupt Controller (NVIC) for configuring priority. scaledNonNegativeInteger 1..1
vendorSystickConfig Indicate whether the processor implements a vendor-specific System Tick Timer. If false, then the Arm-defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0. boolean 1..1
deviceNumInterrupts Add 1 to the highest interrupt number and specify this number in here. You can start to enumerate interrupts from 0. Gaps might exist between interrupts. For example, you have defined interrupts with the numbers 1, 2, and 8. Add 9 :(8+1) into this field. scaledNonNegativeInteger 0..1
sauNumRegions Indicate the amount of regions in the Security Attribution Unit (SAU). If the value is greater than zero, then the device has a SAU and the number indicates the maximum amount of available address regions. scaledNonNegativeInteger 0..1
sauRegionsConfig If the Secure Attribution Unit is preconfigured by HW or Firmware, then the settings are described here. SauRegionsConfigType 0..1

 

/device/cpu/sauRegionsConfig element

Set the configuration for the Secure Attribution Unit (SAU) when they are preconfigured by HW or Firmware.

Example

<device>
...
<sauRegionsConfig protectionWhenDisabled="n">
<region>
...
</region>
...
<region>
...
</region>
</sauRegionsConfig>
...
</device>

The example defines two Secure Attribution Units, which are enabled by default. When the SAU regions are disabled, the protection level is non-secure (n).

/device/cpu/sauRegionsConfig

Parent Element Element Chain
cpu /device/cpu element
Attributes Description Type Use
enabled Specify whether the Secure Attribution Units are enabled. The following values can be used: true,false,1, and 0. xs:boolean optional
protectionWhenDisabled Set the protection mode for disabled regions. When the complete SAU is disabled, the whole memory is treated either "s"=secure or "n"=non-secure. This value is inherited by the <region> element. Refer to element protection for details and predefined values. xs:string optional
Child Elements Description Type Occurrence
region Group to configure SAU regions. xs:string 0..*

 

/device/cpu/sauRegionsConfig/region element

Define the regions of the Secure Attribution Unit (SAU). The protection level is inherited from the attribute <protectionWhenDisabled> of the enclosing element sauRegionsConfig.

Example:

<sauRegionsConfig>
<region name="SAU1">
<base>0x10001000</base>
<limit>0x10005000</limit>
<access>n</access>
</region>
<region enabled="false" name="SAU2">
<base>0x10006000</base>
<limit>0x10008000</limit>
<access>c</access>
</region>
</sauRegionsConfig>

The example defines two secure regions with the names SAU1 and SAU2. SAU1 has the address boundries 0x10001000 and 0x10005000. The region has non-secure access rights. SAU2 has the address boundries 0x10006000 and 0x10008000. The region has secure callable access rights.

/device/cpu/sauRegionsConfig/region

Parent Element Element Chain
sauRegionsConfig /device/cpu/sauRegionsConfig element
Attributes Description Type Use
enabled Specify whether the Secure Attribution Units are enabled. The following values can be used: true and false, or 1 and 0. Default value is true. xs:boolean optional
name Identifiy the region with a name. xs:string optional
Child Elements Description Type Occurrence
base Base address of the region. scaledNonNegativeInteger 1..1
limit Limit address of the region. scaledNonNegativeInteger 1..1
access Use one of the following predefined values to define the acces type of a region:
- n : non-secure
- c : secure callable 		xs:string 1..1